Technical Field
This disclosure relates to non-volatile memory unit and method for manufacturing the same, in particular, to a unit and method that could form an erase gate (EG) with a relative wide base that tapering upward the top, in order to let the floating gate (FG) to insert below portion of the erase gate (EG). Therefore, the rapid erasing effect of particular portion of the electric field could be enhanced.
Related Art
A split gate non-volatile memory unit is widely used in independent and embedded type non-volatile application. Since it has a smaller sector cleaning and a more easily supported circuit design, in the embedded non-volatile IC industry it becomes more and more important. For instance, could be used at the MCU and smartcard.
In previous non-volatile memory units of split gate of the Microchip™ and SST™ are consider to be easily manufactured and have a reliable reliabilities, thus are considered a most approval solution nowadays. In the core of the non-volatile memory unit, double layered polycrystalline silicon layer is consider as the floating gate of the first polycrystalline silicon layer and selective gate of the second polycrystalline silicon layer. As the IC device become smaller and smaller, the double polycrystalline silicon of slit gate could not satisfy the nowadays' trend.
By adding addition polycrystalline silicon layer for couple control gate, the tri-polycrystalline silicon split gate is getting smaller and also gains its importance. In the core of the non-volatile, in this technique, the three-layer polycrystalline silicon is considered as the floating gate of the first polycrystalline silicon layer, the second polycrystalline silicon layer as couple control gate, and the third polycrystalline silicon layer as erase gate/selective gate.
Similar to convention non-volatile memory unit of stacking gate, such as ETOX. First of all, formed the floating gate along the bit line direction, and formed the couple control gate (CG) as mask for etching the floating gate. By back-etching tri-polycrystalline silicon to form the erase gate and the select separator of the erase gate and selective gate. Since the erase gate and select separator includes different gate dielectric for different usage, so the fabrication process of the transistor oxide layer of the selective gate and the tunnel oxide layer have to be carefully consider.
Unfortunately, at the existing split gate structure and manufacturing method the above said request are hard to realize. The dielectric between the floating gate and the selective gate has to integrate to the combination of the tunneling oxide layer, which disposed between the floating gate and the selective gate. Therefore, the manufacturing process will be more complicate and lack of flexibility thus became a closed system. Finally and most importantly, now existing tri-polycrystalline silicon split gate cannot avoid involving etching, and growing of the oxidizing layer with rough surface of the floating gate. The floating gate is used in erasing the nodes. Assume that the surface of the polycrystalline silicon and the tunneling oxide layer are not carefully handle, the uneven micro surface structure of the floating gate polycrystalline silicon will not be able to cause the tunneling effect of the tunnel oxidation layer thus affect the reliability.